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september 2008 rev 1 1/37 AN2787 application note monolithic vr demonstr ation board for chipset and ddr2/3 supply for ultramobile pc (umpc) applications introduction pm6641 demonstration board order code: steval-isa050v1 (previously coded as pm6641eval). the pm6641 demonstration board is a monolithic voltage regulator (vr) module with internal power mosfets, spec ifically designed to supply ddr2/3 memory and chipset in ultramobile pc and real estate constrained portable systems. it integrates three independent, adjustable, constant frequency buck converters, a 2 apk low dropout (ldo) linear regulator, and a 15 ma low-noise buffered reference. each regulator is provided with basic undervoltage (uv) and overvoltage (ov) protections, programmable soft-start and current limit, active soft-end, and pulse skipping at light loads. this document describes all features of the pm6641 demonstration board. figure 1. pm6641 demonstration board www.st.com
contents AN2787 2/37 contents 1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 demonstration kit schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 component assembly and layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 i/o interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 recommended equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.1 jp1 vddq output discharge (dscg pin) . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.2 jp3 switching regulator phase control (set_ph1 pin) . . . . . . . . . . . . . . 15 7.3 jp4 1.8 v (vddq) external/internal divider (vfb_1s8 pin) . . . . . . . . . . . 16 7.4 jp5 1.5 v external/internal divider (vfb_1s5 pin) . . . . . . . . . . . . . . . . . . 17 7.5 jp6 1.05 v external/internal divider (vfb_1s05 pin) . . . . . . . . . . . . . . . . 17 7.6 jp7 current limit (csns pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8 test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9 getting started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 10 steval-isa050v1 evaluation test s . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 10.1 sw regulators turn-on (soft-start) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 10.2 sw regulator - working mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 10.3 load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10.4 load transient responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.5 efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 10.6 phase management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 10.7 fault management (ovp, uvp, uvlo, thermal) . . . . . . . . . . . . . . . . . . . 30 10.8 sw regulators current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.9 soft-end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
AN2787 contents 3/37 10.10 thermal behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
list of figures AN2787 4/37 list of figures figure 1. pm6641 demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. pm6641 demonstration board schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. top side component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. layer 2 view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6. layer 3 view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 7. bottom view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 8. bottom side component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 9. jp1 dscg pin setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 10. jp3 phase control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 11. jp4 1.8 v divider selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 12. jp5 1.5 v divider selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 13. jp6 1.05 v divider selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 14. pm6641 demonstration board programmed current limit vs. csns resistor . . . . . . . . . . . 18 figure 15. jp8 setting switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 16. pm6641 demonstration board test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 17. vddq turn-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 18. vddq, vtt and vttref turn-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 19. pwm mode: vddq output voltage, phase voltage and inductor current, current load = 2.3 a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 20. pulse skip mode: vddq output voltage, phase voltage and inductor current, current load = 0 a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 21. forced pwm mode (soft ov): vddq output voltage, phase voltage, inductor current and power good signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 22. vddq (1.8 v) load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 23. 1.5 v load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 24. 1.05 v load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 25. vtt load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 26. vttref load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 27. vddq, vtt and vttref, vddq load transient response, ivddq = 0 to 2.3 a at 2.5 a/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 28. 1.5 v output voltage and inductor current, 1.5 v rail load transient response, 1.5 v = 0 to 1.25 a at 2.5 a/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 29. 1.05 v output voltage and inductor current, 1.05 v rail load transient response. i1.05 v = 0 to 1.75 a at 2.5 a/s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 30. vddq, vttref, vtt and vtt output current, vtt rail load transient response, ivtt = ?1 a to +1 a at 2.5 a/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 31. sw regulators efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 32. sw regulators phases, 120 deg phase shift. setph1 pin tied to agnd . . . . . . . . . . . . . . 29 figure 33. sw regulators phases, no phase shift - synchronous clock, setph1 pin tied to avcc . . 30 figure 34. vddq, vtt, vttref output voltage, vddq temporarily shorted to 3.3 v, output overvoltage protection triggered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 35. vddq, vtt, vttref output voltage and vddq inductor current, vddq feedback pin temporarily shorted to gnd, output undervoltage protection triggered . . . . . . . . . . . . . . . 31 figure 36. vddq (1.8 v), 1.5 v, 1.05 v output voltage and avcc input power supply, input undervoltage lockout triggered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 37. vddq (1.8 v), 1.5 v, 1.05 v and vtt rails output voltage, thermal shutdown triggered . . 32 figure 38. 1.5 v rail output voltage, 1.5 v inductor current and output current, peak current limit
AN2787 list of figures 5/37 reached . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 39. vddq(1.8 v), vtt and vttref rail output voltage, en_1s8 and en_vtt tied to agnd - soft off with tracking discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 40. vddq(1.8 v), vtt and vttref rail output voltage. en_1s8 and en_vtt tied to agnd - soft off without tracking discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 41. pm6641 demonstration board surface temperature when loaded with typical currents, t amb = 23 c, v in = 3.3 v, f sw = 660 khz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
main features AN2787 6/37 1 main features switching section 0.8 v 1% voltage reference 2.7 v to 5.5 v input voltage range fast response, constant frequency, current mode control three independent, adjustable, smps for ddr2/3 (vddq) and chipset supply s3-s5 states compliant with ddr2/3 section active soft-end for all outputs selectable tracking discharge for vddq separate power good signals pulse skipping at light load programmable current limit and soft-start for all outputs latched ovp, uvp protection thermal protection reference and termination voltages (vttref and vtt) 2 apk ldo for ddr2/3 term ination (vtt) with foldback remote vtt output sensing high-z vtt output in s3 15 ma low-noise ddr2/3 buffered reference (vttref)
AN2787 demonstration kit schematic 7/37 2 demonstration kit schematic figure 2. pm6641 demonstration board schematic c26 0603-100p c4 0805-10u c16 0603-100n c27 0603-100p r10 0603-180k tp8 gnd 1 r20 0603-68k tp6 agnd 1 c28 0603-100p r2 0603-4r3 vin tp16 agnd 1 c18 0603-33n vcc tp15 ldoin 1 c30 0603-100p vcc avcc c19 0603-22n c7 b case - 220u tp4 pg_1s05 1 c31 0603-100p + c13 el smd c-10u 1 2 r33 0603-join avcc tp12 vout_1s05 1 c2 0805-10u avcc r12 0603-47k r3 0603-100k tp14 vtt 1 r4 0603-68k c6 b case - 220u c17 0603-100n tp5 vcc 1 r11 0603-100k + c5 el smd c-10u 1 2 c21 0603-22n r17 0603-68k c25 0603-100p tp1 vttr ef 1 c32 0603-15p jp1 strip 3 1 3 2 r31 0603-join c11 1206-22u 1 2 tp13 gnd 1 jp3 strip 3 1 3 2 r34 0603-join u1 pm6641_qfpn agnd_1 1 set_swf 2 vout_1s8 3 csns 4 sgnd_1s8_1 5 sgnd_1s8_2 6 vsw_1s8_1 7 vsw_1s8_2 8 vin_1s8_1 9 vin_1s8_2 10 vfb_1s8 11 comp_1s8 12 ss_1s8 13 ss_1s05 14 comp_1s05 15 vfb_1s05 16 sgnd_1s05_1 17 vsw_1s05_1 19 vsw_1s05_2 20 vin_1s05_2 22 pg_1s05 23 pg_1s8 24 en_vtt 36 en_1s5 35 en_1s05 34 vin_1s5 33 vsw_1s5_2 32 vsw_1s5_1 31 sgnd_1s5_2 30 sgnd_1s5_1 29 vfb_1s5 28 comp_1s5 27 ss_1s5 26 pg_1s5 25 sgnd_1s05_2 18 vin_1s05_1 21 vcc 48 vtt_fb 47 dscg 46 vttref 45 ldo_in 44 vtt 43 vtt_gnd 42 avcc 41 agnd_2 40 set_ph1 39 agnd_3 38 en_1s8 37 th er mal 49 avcc l2 2839-1u5 1 2 c23 0603-470p l3 2839-1u 1 2 r19 0603-68k + c8 el smd c-10u 1 2 tp18 aux 1 c33 0603-15p c12 0805-10u tp2 pg_1s8 1 avcc tp7 vin 1 c15 b case - 220u c22 0603-330p c20 0603-22n c1 0603-1u jp4 strip 3 1 3 2 l1 2839-1u 1 2 r5 0603-150k jp5 strip 3 1 3 2 r7 0603-100k r8 0603-120k r32 0603-join + c14 el smd c-10u 1 2 avcc tp10 vout_1s5 1 tp3 pg_1s5 1 c34 0603-15p aux aux tp9 vout_1s8 1 r21 0603-68k r6 0603-120k r22 0603-68k jp7 strip 2 1 2 r30 0603-join r13 0603-68k aux tp17 gnd 1 c3 0805-10u r23 0603-68k jp8 strip 2 1 2 sw1 sw dip-4 1 2 3 4 5 6 7 8 vin c24 0603-330p c9 b case - 220u r18 0603-68k c10 b case - 220u r1 0603-4r3 tp11 gnd 1 vin c29 0603-100p jp6 strip 3 1 3 2 r9 0603-56k
bill of material AN2787 8/37 3 bill of material table 1. pm6641 demonstration board list of components qty component description package part number mfr value note 1c1 ceramic, 10 v, x5r, 20% smd 0603 standard 1 4 c2, c3, c4, c12 ceramic, 10 v, x5r, 20% smd 0805 grm21br61a106ke19 murata 10 4 c5, c8, c13, c14 smd c case n.m. 5 c6, c7, c9, c10, c15 ceramic, 4 v, x5r, 20% smd 1206 amk316bj107ml taiyo yuden 100 1c11 ceramic, 6.3 v, x5r, 10% smd 1206 grm31cr60j226ke19 murata 22 2 c16, c17 ceramic, 16 v, x7r, 10% smd 0603 standard 100 n 1c18 ceramic, 25 v, x7r, 10% smd 0603 grm188r71e333ka01 murata 33 n 3 c19, c20, c21 ceramic, 16 v, x7r, 10% smd 0603 standard 22 n 2 c22, c24 ceramic, 50 v, c0g, 5% smd 0603 standard 330 pf 1c23 ceramic, 50 v, c0g, 5% smd 0603 standard 470 pf 4 c25, c26, c27, c28 ceramic, 50 v, c0g, 5% smd 0603 standard 100 pf 3 c29, c30, c31 ceramic, 50 v, c0g, 5% smd 0603 n.m. 3 c32, c33, c34 ceramic, 50 v, c0g, 5% smd 0603 n.m. 2r1, r2 chip resistor, 0.1 w, 1% smd 0603 standard 3r3 1r3 chip resistor, 0.1 w, 1% smd 0603 standard 100 k ? 9 r4, r13 r17, r18, r19, r20, r21, r22, r23 chip resistor, 0.1 w, 1% smd 0603 standard 68 k ? 1r16 chip resistor, 0.1 w, 1% smd 0603 n.m. 1r5 chip resistor, 0.1 w, 1% smd 0603 standard 150 k ?
AN2787 bill of material 9/37 2r6, r8 chip resistor, 0.1 w, 1% smd 0603 standard 120 k ? 1r7 chip resistor, 0.1 w, 1% smd 0603 standard 100 k ? 1r9 chip resistor, 0.1 w, 1% smd 0603 standard 56 k ? 1r10 chip resistor, 0.1 w, 1% smd 0603 standard 180 k ? 1r11 chip resistor, 0.1 w, 1% smd 0603 standard 100 k ? 1r12 chip resistor, 0.1 w, 1% smd 0603 standard 47 k ? 3 r32, r33, r34 chip resistor, 0.1 w, 1% smd 0603 standard 0 ? short 2 r30, r31 chip resistor, 0.1 w, 1% smd 0603 n.m. 2 l1, l3 smt 11arms, 9.5 m ? smd 2827 744312100 /lf wrth 1.0 h 1l2 smt 9 arms, 10.5 m ? smd 2827 744312150 /lf wrth 1.5 h 1 u1 ic vr - 48-pin vfqfpn 7x7 pm6641 stmicroelectronics 5 jp1, jp3, jp4, jp5, jp6 header, 3-pin sip3 2 jp7, jp8 header, 2-pin sip2 5 tp1, tp2, tp3, tp4, tp18 header, single pin 13 tp5, tp6, tp7, tp8, tp9, tp10, tp11, tp12, tp13, tp14, tp15, tp16, tp17 test point 1 sw1 switch 4-spst dip-8 standard table 1. pm6641 demonstration board list of components (continued) qty component description package part number mfr value note
component assembly and layout AN2787 10/37 4 component assembly and layout figure 3. top side component placement figure 4. top view
AN2787 component assembly and layout 11/37 figure 5. layer 2 view figure 6. layer 3 view
component assembly and layout AN2787 12/37 figure 7. bottom view figure 8. bottom side component placement
AN2787 i/o interface 13/37 5 i/o interface the pm6641 demonstration board has the following test points given in ta bl e 2 . table 2. pm6641 demonstration board input/output interface test point description vcc (tp5) +5 v ic supply, positive terminal ldoin (tp15) ldo (vtt) linear regulator input power supply aux (tp18) auxiliary 3.3 v for pull-up (not required) agnd (tp6, tp16) vcc, ldo, vt t and vttref common return vin (tp7) power supply input voltage positive terminal gnd (tp8, tp11, tp13, tp17) power supply and switching regulator outputs common return v1s8 (tp9) 1.8 v (vddq) switching regulator output v1s5 (tp10) 1.5 v switching regulator output v1s05 (tp12) 1.05 v switching regulator output vtt (tp14) ldo (vtt) li near regulator output vttref (tp1) voltage reference (vttref) buffer output pg1s8 (tp2) 1.8 v (vddq) switchin g regulator power good signal pg1s5 (tp3) 1.5 v switching regulator power good signal pg1s05 (tp4) 1.05 v switching regulator power good signal
recommended equipment AN2787 14/37 6 recommended equipment 5 v power supply 3.3 v, 20 w power supply active loads digital multimeters 500 mhz four-trace oscilloscope
AN2787 configuration 15/37 7 configuration the pm6641 demonstration board allows the user to test all the main features of the vr pm6641, acting on 7 di fferent jumpers and 4 switches. sw1 (4 spst switches) lets the user enable the switching regulators and the vtt linear regulator. in the following sections each jumper is analyzed. 7.1 jp1 vddq output discharge (dscg pin) the jp1 jumper is used to choose between the tracking discharge or nontracking discharge of the 1.8 v rail (vddq) output. when the 1.8 v rail is deactivated (en_1s8 goes low) and the dscg is set high, tracking discharge takes place: the 1.8 v rail regulator is discharged by the internal mosfets the 0.9 v ldo and vttref work tracking with half of the 1.8 v rail when the 0.9 v ldo and vttref reach a voltage threshold of about 300 mv, the nontracking discharge mode is performed by closing the internal discharge mosfets. if the nontracking discharge mode is chosen, when en_1s8 goes low, the 1.8 v and 0.9 v rails and the vttref buffer are independently discharged by internal mosfets. figure 9. jp1 dscg pin setting 7.2 jp3 switching regulator phase control (set_ph1 pin) the jp3 jumper allows selecting two different oscillator settings in order to change the delay between the pulses that start the control cycle. the inner clock is divided in order to obtain three slower clocks with a fixed delay of 120 deg. by setting jp3 as depicted in figure 10 , it is possible to synchronize the 1.8 v, 1.5 v and 1.05 v switching regulator clocks or to select 120 deg delay in order to decrease the total rms input current. non tracking discharge tracking discharge
configuration AN2787 16/37 figure 10. jp3 phase control the 120 deg phase shifting is the default configuration in which the inner clock is divided and three pulses delayed by 120 deg are obtained to trigger the switching regulator loops. the synchronous clocking allows all the regulators to start at the same pulse, avoiding the jitter due to simultaneous turn-on and off of different sections, but increasing the overall rms input current. 7.3 jp4 1.8 v (vddq) externa l/internal divider (vfb_1s8 pin) the jp4 jumper allows selecting the internal divider or the external divider for the 1.8 v switching regulator. when the vfb_1s8 pin is connected directly to the output capacitor, the internal divider is enabled and this section provides 1.8 v output voltage. when the multifunction pin vfb_1s8 is tied to the central tap of an external divider, the switching regulator becomes adjustable, with the following output voltage: equation 1 figure 11. jp4 1.8 v divider selection 120deg phase shifting synchronous jp3 v 8 . 0 1 r r vout 6 5 ? ? ? ? ? ? ? ? ? + = internal divider enabled external divider enabled
AN2787 configuration 17/37 7.4 jp5 1.5 v external/internal divider (vfb_1s5 pin) the jp5 jumper allows selecting the internal divider or the external divider for the 1.5 v switching regulator. when the vfb_1s5 pin is c onnected directly to the output capacitor, the internal divider is enabled and this sectio n provides 1.5 v output voltage. when the multifunction pin vfb_1s5 is tied to the central tap of an external divider, the switching regulator becomes adjustable, with the following output voltage: equation 2 figure 12. jp5 1.5 v divider selection 7.5 jp6 1.05 v external/inte rnal divider (vfb_1s05 pin) the jp6 jumper allows selecting the internal divider or the external divider for the 1.05 v switching regulator. when the vfb_1s05 pin is connected directly to the output capacitor, the internal divider is enabled and this sect ion provides 1.05 v output voltage. when the multifunction pin vfb_1s5 is tied to the central tap of an external divider, the switching regulator becomes adjustable, with the following output voltage: equation 3 figure 13. jp6 1.05 v divider selection v 8 . 0 1 r r vout 8 7 ? ? ? ? ? ? ? ? ? + = external divider enabled internal divider enabled v 8 . 0 1 r r vout 10 9 ? ? ? ? ? ? ? ? ? + = internal divider enabled external divider enabled
configuration AN2787 18/37 7.6 jp7 current limit (csns pin) each switching regulator curren t limit is set by inserting a resistor between the csns pin and agnd. by changing this resistor value, all the current limits change, as shown in figure 14 . figure 14. pm6641 demonstration board programmed current limit vs. csns resistor if the csns pin is tied to avcc, the current lim it is set through the inner reference resistor (equal to 50 k ? ). figure 15. jp8 setting switching frequency peak current limit 0,00 1,00 2,00 3,00 4,00 5,00 6,00 7,00 50 70 90 110 130 150 170 rcsns [kohm] current limit [a] cl_1v8 cl_1v5 cl_1v05 adjusted switching frequency default switching frequency
AN2787 test setup 19/37 8 test setup figure 16 shows the suggested setup connections between the pm6641 demonstration board, the loads, and the external supply. figure 16. pm6641 demonstration board test setup
getting started AN2787 20/37 9 getting started the following step-by-step power-up and power-down sequences are provided in order to correctly evaluate the pm6641 demonstration board performance. power-up sequence connect power supplies as shown in the pm6641 demonstration board test setup ( figure 16 ) and insert the meters in order to perform the desired performance evaluation. connect the scope-probes as desired set the jp1 through jp8 jumpers in orde r to properly configure the pm6641 demonstration board. set the sw1 switc hes (en_1s8, en_vtt, en_1s5, en_1s05) to the on position. do not change jump er settings when the board is powered set the vcc supply to 5 v 5% and the current limit to 100 ma set the vin supply to a voltage in the range 2.7 v to 3.6 v set all active loads to 0 a turn-on the vin supply turn-on the vcc supply vary the 1.8 v (vddq) load from 0 a to 4 a vary the 1.5 v load from 0a to 2.5 a vary the 1.05 v load from 0a to 3.5 a vary the 0.9 v (vtt) load from 0 a to 2 a to test source capability. to test sink capability use the alternative vtt load connection shown in figure 16 vary vttref load to test source capabilty. power-down sequence decrease vttref and vtt loads to 0 a turn-off the 1.8 v (vddq), 1.5 v, 1.05 v loads decrease vcc supply from 5 v to 3.8 v in order to test the input undervoltage lockout (uvlo) increase vcc supply from 3.8 v to 5 v to restart the device use the en_1s8 and en_vtt switches to enter/exit the s0-s3-s5 states turn-off the vcc supply turn-off the vin supply.
AN2787 steval-isa050v1 evaluation tests 21/37 10 steval-isa050v1 evaluation tests 10.1 sw regulators turn-on (soft-start) when the en_xx pin is toggled high, the corres pondent sw regulator performs the soft-start as programmed through the external soft-start capacitor. figure 17 depicts vddq (1.8 v) turn-on with c ss = 22 nf. figure 17. vddq turn-on
steval-isa050v1 evaluation tests AN2787 22/37 figure 18. vddq, vtt and vttref turn-on 10.2 sw regulator - working mode each switching regulator changes working mode with the appropriate load. when the load is heavy, the sw enters pwm mode, but when the lo ad is light, pulse skip mode is entered. each sw regulator is also able to sink cu rrent from the output (forced pwm mode when a soft overvoltage occurs).
AN2787 steval-isa050v1 evaluation tests 23/37 figure 19. pwm mode: vddq output voltage, phase voltage and inductor current, current load = 2.3 a
steval-isa050v1 evaluation tests AN2787 24/37 figure 20. pulse skip mode: vddq output voltage, phase voltage and inductor current, current load = 0 a figure 21. forced pwm mode (soft ov): vddq output voltage, phase voltage, inductor current and power good signal
AN2787 steval-isa050v1 evaluation tests 25/37 10.3 load regulation figure 22. vddq (1.8 v) load regulation figure 23. 1.5 v load regulation
steval-isa050v1 evaluation tests AN2787 26/37 figure 24. 1.05 v load regulation figure 25. vtt load regulation figure 26. vttref load regulation
AN2787 steval-isa050v1 evaluation tests 27/37 10.4 load transient responses figure 27. vddq, vtt and vttref, vddq load transient response, ivddq = 0 to 2.3 a at 2.5 a/s figure 28. 1.5 v output voltage and inductor current, 1.5 v rail load transient response, 1.5 v = 0 to 1.25 a at 2.5 a/s
steval-isa050v1 evaluation tests AN2787 28/37 figure 29. 1.05 v output voltage and inductor current, 1.05 v rail load transient response. i 1.05 v = 0 to 1.75 a at 2.5 a/s figure 30. vddq, vttref, vtt and vtt output current, vtt rail load transient response, i vtt = ?1 a to +1 a at 2.5 a/s
AN2787 steval-isa050v1 evaluation tests 29/37 10.5 efficiency figure 31. sw regulators efficiency 10.6 phase management figure 32 and 33 show the sw regulators loaded with 1.3 a (vddq rail), 1.25 a (1.5 v rail) and 1.75 a (1.05 v rail). by connecting the setph1 pin to agnd or to avcc the following two different phase shifts are allowed. figure 32. sw regulators phases, 120 deg phase shift. setph1 pin tied to agnd
steval-isa050v1 evaluation tests AN2787 30/37 figure 33. sw regulators phases, no phase shift - synchronous clock, setph1 pin tied to avcc 10.7 fault management (ovp, uvp, uvlo, thermal) each switching regulator is able to detect the output overvoltage and undervoltage. when the ov is detected the high-side mosfet is turned off and the low-side mosfet is turned on. when the uv is detected, the power mosfets are both turned off and the discharge mosfet is turned on (soft-end). the soft-end is also performed when the junction temperature is higher than 150 c. figure 34. vddq, vtt, vttref output voltage, vddq temporarily shorted to 3.3 v, output overvoltage protection triggered
AN2787 steval-isa050v1 evaluation tests 31/37 figure 35. vddq, vtt, vttref output voltage and vddq inductor current, vddq feedback pin temporarily shorted to gnd, output undervoltage protection triggered when the input undervoltage is detected, the vddq (1.8 v) rail performs the output voltage soft-end. the 1.5 v and 1.05 v rails turn-off the high-side power mosfet and turn-on the low-side one.
steval-isa050v1 evaluation tests AN2787 32/37 figure 36. vddq (1.8 v), 1.5 v, 1.05 v output voltage and avcc input power supply, input undervoltage lockout triggered figure 37. vddq (1.8 v), 1.5 v, 1.05 v and vtt rails output voltage, thermal shutdown triggered
AN2787 steval-isa050v1 evaluation tests 33/37 10.8 sw regulators current limit cycle-by-cycle the high-side mo sfet current is monitored and if it's higher than the programmed current limit, the high-side mosfet is immediately turned off. figure 38. 1.5 v rail output voltage, 1.5 v inductor current and output current, peak current limit reached 10.9 soft-end each sw regulator, when turned off, performs the output voltage soft-end by turning off the power mosfet and turning on the discharge mosfet. when the output voltage is lower than about 300 mv, the low-side power mosfet is turned on. vttref and vtt can track half of vddq also during the soft off. these rails are allowed two different modes of discharge: tracking and nontracking discharge.
steval-isa050v1 evaluation tests AN2787 34/37 figure 39. vddq(1.8 v), vtt and vttref rail output voltage, en_1s8 and en_vtt tied to agnd - soft off with tracking discharge figure 40. vddq(1.8 v), vtt and vttref rail output voltage. en_1s8 and en_vtt tied to agnd - soft off without tracking discharge
AN2787 steval-isa050v1 evaluation tests 35/37 10.10 thermal behavior the device temperature is mainly influenced by ldo vtt current. the typical working currents are shown in ta b l e 3 . vtt is supplied by vddq and the device (average) temperature is 54.5 c. figure 41. pm6641 demonstration board surface temperature when loaded with typical currents, t amb = 23 c, v in = 3.3 v, f sw = 660 khz table 3. average working currents for each rail rail current [a] vddq (1.8 v) 1.35 1.5 v 1.25 1.05 v 1.75 vtt (0.9 v) 0.3
revision history AN2787 36/37 11 revision history table 4. document revision history date revision changes 05-sep-2008 1 initial release
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